The present invention relates to interrupt processing techniques employed within a computer system and more specifically, to a method and apparatus for rapidly identifying the source of an interrupt. In digital systems employing processors, normal program execution is halted to respond to the detection of either an asynchronous or a synchronous event, which may be associated with a peripheral device. Upon the occurrence of such an event, an interrupt signal is generated to provide an indication to the processor that the peripheral device requires service. Typically, the interrupt signals of various peripheral devices are wire OR'd together since the number of interrupt events that may need to be accommodated can exceed the number of interrupt signals that are supported by present processors. Often there are several interrupt signals going directly to the processor, however, even where multiple interrupt signals are employed the interrupt cannot be classified based solely upon the interrupt signal alone. The processor, upon detection of an interrupt via the assertion of an interrupt signal, vectors to an interrupt handler, and, using standard bus accesses, determines the source of the interrupt by testing interrupt bits associated with devices capable of triggering the relevant interrupt signal. After, or during servicing of the interrupt, the processor uses standard bus accesses to clear the source of the interrupt and thereby re-arm the system.
In conventional processing systems, the execution of the above described tasks wastes considerable time in determining the source of the interrupt and later, in clearing the interrupt, due to the number of bus accesses that are required during the interrupt handling process. The overhead is the result of the intrinsic latency of the bus as well as delays incurred in reading and writing buffers, which are electrically situated between the processor and the bus.
It would therefore be desirable to have a technique for determining the source of an interrupt, which avoids the latency, associated with traditional interrupt detection mechanisms.